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Place commands

Here is a list of all commands which you can find inside the menus. The following entries have to be used to place devices like lines, circles, text labels, transistors, resistors, pins etc. :

text: Place text label. circle, rect, line, cont, econt, sline: Placing circles, rectangles, lines, contacts, extended contacts , multiple segment lines.
nmos, pmos, n4mos, p4mos : MOS Transistors
nbip, pbip, n4bip, p4bip : Bipolar Transitors
arsc : SPICE3 arbitrary source
vdc, idc : DC current and voltage source
vsin, isin : current and voltage source with sinusoidal transient characterictics.
vpul, ipul : current and voltage source with pulse transient characterictics.
vpwl, ipwl : current and voltage source with piecewise linear transient characterictics.

vexp, iexp : current and voltage source with exponential transient characterictics.

vsffm, isffm : current and voltage source with frequency modulation transient characterictics.

vcvs, vccs, cccs, ccvs: Linear voltage and current controlled voltage and current sources.
_vcvspoly, _vccspoly, _cccspoly, _ccvspoly: Voltage and current controlled voltage and current sources with POLY characteristics (old SPICE2 stuff), but necessary for the inclusion of opamp of other macromodels.

res, cap, ind : linear resistor, capacitor and inductance.
sem. cap, sem. res : linear semiconductor capacitor and resistor.

mutind, trline, trloss, rcline : mutual coupled inductance, lossy and lossless lines
vswit, iswit, diode: voltage and current controlled switch, diode
njfet, pjfet, nmesfet, pmesfet : JFETs and MESFETs.

frame: Nice frame to generate good looking schematic plots for customers.

inport : create input port to define connections between different schematic hierarchy levels .
outport : create input port to define connections between different schematic hierarchy levels .
ioport : create input port to define connections between different schematic hierarchy levels .

named pin : create pin for local named connections (connections between different nets which are attached to named pins of the same name)

vss, vdd, vss1, vdd1: Global pins.

gnd: Global pin ground (node 0), must appear at least once in the schematic hierarchy (and on the top level).

named global : If the number of pre-defined globals vss, vdd, vss1, vdd1 is not sufficient for your design, you can create more globals with arbitrary names. The only restriction is that every global must appear at least once on the top level schematic. To satisfy this requirement, you can connect the named global on top level with 1GOhm resistor to whatever you want .

options : Places simulation box which generates a .options - statement during netlisting.

params: Box which stored user-defined design variables.

projectnote: Box stores notes.

dcop: Places simulation box which generates a .op -statement during netlisting.

dcsweep: Places simulation box which generates a .dc -statement during netlisting.

smallsig: Places simulation box which generates a .ac -statement during netlisting.

noise: Places simulation box which generates a .noise -statement during netlisting.

tran: Places simulation box which generates a .tr -statement during netlisting.

four: Places simulation box which generates a .four -statement during netlisting.

paramsweep: Places simulation box which controls a variable parametric sweep.

monte carlo: Places simulation box which controls a monte carlo simulation.

optimization: Places simulation box which controls an optimization .

temp: Places simulation box which controls a temperature sweep .


next up previous contents
Next: Schematic menu Commands Up: Command Index Previous: Command Index
Martin Maschmann
1999-10-10