Ver Structural Verilog Compiler
One of the included examples showing a visual example of the output of Cyco, the cycle-simulation compiler when simulating a line-drawing unit. Its netlist was converted into levelized C code that executes in real-time. For its Verilog sourcecode, click here.

Click here to download Ver-1.3.36 for Unix.
Click here to view a draft version of the docs for just the compiler itself and not the support packages.
Click here to view the documentation for the behavioral extensions added to Ver and Cyco by Paul Stravers.
Click here to view the change log for all of the included packages.
Click here to view supplemental notes for this distribution.
Click here for information on Vertex: a new, freely-distributable Verilog parser.
Click here to view the documentation for VCDScan.
Click here to see GTKWave in action.


Hey Peoples!

Welcome to Ver Structural Verilog Compiler. I created this because I saw a need for a portable, lightweight Verilog compiler that doesn't have the sourcecode size limits of the VeriWell training simulator. Note that this is a structural compiler. Behaviorals (initial/always) are not completely supported in the compiler's parser at this time and there is no timetable set to support them completely as the intention of Ver is to produce synthesizable netlists out of Verilog sourcecode. To this end, most structural constructs are supported, and some highly useful behavioral constructs are supported thanks to the efforts of Paul Stravers.

Ver's simulation methodology relies on using C programs that interface with the simulator. It's much faster and it's probably the best way to simulate logic since the cycle simulator compiler (Cyco) has the ability to generate efficient, branchless C code. Run the fifo example to get an idea of how fast Cyco really is when it simulates two-state logic.

For event simulation fans, the behavioral updates have not found their way into the event simulator VSIM. Most likely, VSIM will become deprecated in favor of CSIM, the Multivalue Cycle Simulator, and ESIM, the Multivalue Event Simulator. CSIM is a stepping stone to ESIM which will sport near cycle simulator performance because it will be based on the CSIM engine. (ESIM is not available yet, however CSIM is present in the Ver package.) For the time being, check out the fifo_csim example to see how flexible writing testcases under CSIM is. The facility (bit/bitvector) management functions provided by CSIM are quite "programmer friendly."

Look in the "examples" directory to get an idea of what the compiler can do. Any peculiarities/limitations in syntax will be noted in comment lines in the example Verilog sourcecode. I still have to work on making the parser a little more flexible like "really" allowing parameters and things like that. For the time being, the use of vbpp in the experimental directory should suffice.

The event simulator bundled with this is from the VHDL simulator VSIM from the University of Pittsburgh. As its authors say:

VSIM Fine Print
This software is distributed on an as-is basis with no warranty implied or intended. No author or distributor takes responsibility to anyone regarding its use of or suitability. The software may be distributed and modified freely for academic and other non-commercial use but may NOT be utilized or included in whole or part within any commercial product.

...as stated earlier, once ESIM is available, VSIM will be deprecated.

Anna, the older wave analyzer bundled in this package contains huge chunks of code from the IRSIM simulator. (The graphical front end was ripped from IRSIM and adapted for aet [all events trace] viewing.) As such, most of Anna is copyright by Stanford University. Most of my development is done under NetBSD Amiga, Linux on the PC, and AIX on the RS/6000, so Anna should more or less work on those three platforms. Any misbehaving can be traced to the event.c file. If all options fail in event.c and Anna still doesn't work, try to use BSD semantics for the signal handling as I do for Linux. (See the __linux__ ifdef's in event.c.) And if that still doesn't work, use GTKWave because it's heaps better, is GPL'd, and is still under development. =)

As far as the sourcecode goes, you can do with it whatever you feel like. But if you do anything interesting, please let me know because I may find what you've done useful for inclusion in the distribution.

Well, that's about it for now. Have fun!


22sep02 bybell@linux-workshop.com / bybell@nc.rr.com