Miscellaneous Notes
Ver will "flatten" your design out and not include unused modules in
the flattened (.ivf) file. However, the algorithm used to determine the
topmost module requires that the module has to instantiate at least one
component inside of it (and the module itself isn't instantiated
elsewhere). If this doesn't find your module or you want to flatten from
a different one, use the -f flag. (ver -h will show you the other
compile flags.)
No signals are optimized out. You have to run the .ivf file through
Cyco with the -w flag if you want an optimized .ivf model. Of course an
unoptimized model causes some very long signal names, but the positive
side of this is that you can use two signal names to refer to the same
signal. (You can see both sides of a bus, wire, etc.) The down side of
this is that simulation time increases since VSIM has to keep track of
more nodes. As indicated elsewhere in this document, canned storage
elements are provided for cycle simulation to alleviate this problem.
If long simulation times are an issue with larger models, use Cyco
to generate a C code model. It's your responsibility to
multiplex facilities (signals) into and out of the model. See the
cla-cycle and lines-cycle examples.
It is not difficult to convert Ver so it writes out BDNET format files
for logic synthesis. The ability to write out either flattened or
hierarchical designs with fanin/out testing may be in a future version of
Ver. It depends on how motivated I get with this project. =) Cyco does
accurate fan counts now (assuming you run a -w optimized .ivf model
through it), so a future version should be able to calculate capacitive
loading effects and such when standard cell technology libraries
(forthcoming) are supplied.
CONSTX and CONSTZ gates will compile but the cycle simulator cannot
handle them. Multilevel logic isn't handled in Cyco yet since that would
double the runtime of a model. (The X/Z part has to be calculated as well
in a "stacked" logic definition: 0=%00, 1=%01, X=%10, Z=%11.)
VSIM has been mutilated. It now handles 0, 1, X, Z logic.
When compiling VSIM, if your compiler doesn't find the ftime()
function (it's in libcompat on my Amiga running NetBSD; your location may
be different), do a "man ftime" to find out where you have to point the
Makefile in VSIM to link it in. (i.e., -lbsd, -lcompat, etc.)
Assertions, etc. would probably be nice in VSIM. Also, restarting
simulation from any arbitrary point in an aet could prove useful. (You
can "back out" of a simulation and go down a different path this way.)
It's hard to say what I would like to add to VSIM since I'm concentrating
on Cyco at this point.
To view aet's, run anna on the .aet and .wav (optional) files for
your design. Look in the examples directory to see how to do this.
Also, invoking anna without command line arguments will give you the
command usage.
Compiling anna on PPC AIX boxes requires you to "tell" the compiler
that it is SYS_V. (The signal() function never gets called otherwise.)
mem.c in anna uses etext(). This is missing under AIX. Use the MIPS
patch shown in the mem.c code instead.
Faaast cycle simulation has been realized with Cyco, the cycle
compiler. IVF files can be compiled into C code! I've kept VSIM since
Cyco chucks away all timing information and uses strict combinational
circuits (detecting data dependencies and sorting the generated c code as
necessary). Tracing has been completely revamped and is much faster now.
Thanks goes out to Dr. Patrick Madden of SUNY Binghamton for the new and
improved tracing algorithm!
In examples/lines-cyco, you'll find an example of how to use Cyco. It
generates an x-windows front end so you can see what's going on.
Use Gen for numeric macro expansion for repetitive signal instances,
declarations, etc. Look at the test* files in the gen directory to see
what it can do. A couple of files do things like figure out GCD's, etc.
It's quite fast too since the "interpreting" is a nothing more than a
recursive syntax treewalk on the tree of structs the parser creates. (See
gen/exec.c to see what I mean.)
In the future I'll add combinational circuit extraction to Cyco so that
tools like espresso/misII/sis (or a mapper supplied with a future version
of Ver) can be run on the chunks for technology mapping and synthesis.
The extraction isn't hard--there's just a lot going on in this project and
it's not my top priority!
Quine-McCluskey is being worked on (I have the prime implicant,
essential PI routines working but have to do maximal irredundant cover)
for truth table directive expansion and such in Gen. Depending on how the
espressoII coding goes, QM may never see the light of day in a Ver
release. I've been putting it off for a while and working on Ver's parser
instead.
GTKWave has replaced anna. Anna will be kept in the
distribution for use when GTK+ is not available.
If the auto-resizing in GTKWave gets bothersome after a while, just
click on the hpane knob between the signal and wave windows then press
Alt-0.
To import whole signal hierarchies into the GTKWave, bring up the
"Signal Search Tree," highlight the hierarchy you wish to import, then
press either "bundle up" or "bundle down." Press enter for the vector
name and the whole hierarchy will be imported into the viewer.
All the major datatypes for GTKWave are defined in analyzer.h. So
if you have any problems, check there first.
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