Introduction
Welcome to the homepage for Vertex, a freely distributable Verilog parser. The intended use of Vertex is a compiler front-end which generates syntax trees for semantic analysis.
This pre-release is quite early in development and is of limited functionality:
Excluding the lack of specify blocks, the grammar is basically the same one found here. Various additions and changes were made by consulting Thomas and Moorby's The Verilog Hardware Description Language (third edition) as an additional reference. I have just received the IEEE-1364 LRM, so I can concentrate on specification compliance shortly.
Requirements
The file verilog.g inside of the distribution is an LL(2) ANTLR grammar that requires PCCTS to compile. Note that you will have to edit the makefile in order to get it to compile on your platform. The rest of the files in the distribution are straight C code.
Notes
For those who do not wish to develop their own compiler, a freely-distributable Verilog compiler (structural subset), event and cycle simulator, and wavetracer may be found here as the Ver-1.0 package. I plan on supporting Ver, but the focus of my energy in the future will be on developing Vertex such that it is 1364 compliant.